FIG. 1A is a schematic circuit diagram illustrating a temperature detecting device according to the prior art. As shown in FIG. 1A, four resistors r1, r2, r3 and r4 are serially connected between a reference voltage (Vref) and a ground terminal. The reference voltage (Vref) does not vary with temperature. The three nodes between these four resistors are respectively connected to negative input terminals of three comparators 102, 104 and 106 for providing three voltages Vtmp2, Vtmp1 and Vtmp0. The positive input terminals of the comparators 102, 104 and 106 are connected to a PTAT (proportional to absolute temperature) voltage Vptat. The PTAT voltage Vptat increases as the temperature rises. An encoder 110 is connected to the output terminals of the comparators 102, 104 and 106. By the encoder 110, a three-bit thermometer code is converted into a binary code (B1, B0).
FIG. 1B is a schematic diagram illustrating the relationship between the PTAT (proportional to absolute temperature) voltage and the temperature. In a case that the temperature is lower than TMP0, the PTAT voltage Vptat is lower than Vtmp0, and the three bits (T2, T1, T0) at the output terminals of the comparators 102, 104 and 106 are (0, 0, 0). In a case that the temperature ranges between TMP0 and TMP1, the PTAT voltage Vptat ranges between Vtmp0 and Vtmp1, and the three bits (T2, T1, T0) at the output terminals of the comparators 102, 104 and 106 are (0, 0, 1). In a case that the temperature ranges between TMP1 and TMP2, the PTAT voltage Vptat is ranged between Vtmp1 and Vtmp2, and the three bits (T2, T1, T0) at the output terminals of the comparators 102, 104 and 106 are (0, 1, 1). In a case that the temperature is higher than TMP2, the PTAT voltage Vptat is higher than Vtmp2, and the three bits (T2, T1, T0) at the output terminals of the comparators 102, 104 and 106 are (1, 1, 1).
In other words, the three bits T2, T1 and T0 at the output terminals of the comparators 102, 104 and 106 constitute a three-bit thermometer code. By the encoder 110, the three-bit thermometer code is converted into a binary code (B2, B1). FIG. 1C is a schematic diagram illustrating a conversion table of the encoder 110.
However, the temperature detecting device of FIG. 1A has too many comparators, which occupy much layout area of the chip and increase the fabricating cost of the chip. Moreover, the temperature detecting device of FIG. 1A needs an encoder for converting the three-bit thermometer code into a binary code.
FIG. 2A is a schematic circuit diagram illustrating a temperature detecting device having a single comparator according to the prior art. The temperature detecting device of FIG. 2A is disclosed in for example U.S. Pat. No. 4,213,125. As shown in FIG. 2A, five resistors R1, R2, R3, R4 and R5 are serially connected between a power source voltage V and a ground terminal. The power source voltage V does not vary with temperature. The four nodes between these five resistors provide four voltages V1, V2, V3 and V4, respectively. These four voltages V1, V2, V3 and V4 are respectively inputted into the first terminals of switches (SW) 215, 216, 217 and 218. The second terminals of the switches 215, 216, 217 and 218 are all connected to a positive input terminal of a comparator 214.
A resistor R and a thermistor TH are interconnected between the power source voltage V and the ground terminal in series. A node between the resistor R and the thermistor TH provides a voltage V10, which is inputted into a negative input terminal of the comparator 214.
Two inverters 201, 202, a resistor 203 and a capacitor 204 constitute an oscillation circuit to generate an oscillation signal φ. The oscillation signal φ is inputted into first input terminals of four AND gates 206, 207, 208 and 209. In addition, after the oscillation signal φ is received by a counter 205, the counter 205 outputs a first signal φ1, a second signal φ2, a third signal φ3 and a fourth signal φ4. The first signal φ1, the second signal φ2, the third signal φ3 and the fourth signal φ4 are respectively inputted into second input terminals of the AND gates 206, 207, 208 and 209, and respectively inputted into the control terminals of the switches (SW) 215, 216, 217 and 218.
The input terminals of the latches 210, 211, 212 and 213 are connected to the output terminal of the comparator 214. The control terminals of the latches 210, 211, 212 and 213 are respectively connected to the output terminals of the AND gates 206, 207, 208 and 209.
FIG. 2B is a schematic timing waveform diagram illustrating the relationships between the oscillation signal φ, the first signal φ1, the second signal φ2, the third signal φ3 and the fourth signal φ4 processed by the temperature detecting device of FIG. 2A. The latches 210, 211, 212 and 213 generate output signals OUT11, OUT12, OUT13 and OUT14, respectively. In addition, the output signals OUT11, OUT12, OUT13 and OUT14 are renewed every detecting cycle τ.
Due to the characteristics of the thermistor TH, the resistance of the thermistor TH increases with increasing temperature. That is, the higher the temperature is, the lower the voltage V10 is. During every detecting cycle τ, the voltage V10 is sequentially compared with the voltages V1, V2, V3 and V4, and the comparing results are respectively stored in the latches 210, 211, 212 and 213. In this situation, the output signals OUT11, OUT12, OUT13 and OUT14 of the latches 210, 211, 212 and 213 are the output signals of the temperature detecting device.
As the temperature gradually increases from low to high, the output signals OUT11, OUT12, OUT13 and OUT14 of the latches 210, 211, 212 and 213 are sequentially changed from “0000” to “0001”, “0011”, “0111”, “1111”. Since the output signals constitute a four-bit thermometer code, an additional encoder is necessary to convert the thermometer code into a binary code.
FIG. 3A is a schematic circuit diagram illustrating another temperature detecting device having a single comparator according to the prior art. The temperature detecting device of FIG. 3A is disclosed in for example U.S. Pat. No. 7,171,327. A temperature reference network 370 comprises six resistors 378, 380, 382, 384, 386, 388, and a trimmer 390, which are interconnected between a reference voltage (Vref) and a ground terminal is series. The five nodes between these six resistors 378, 380, 382, 384, 386 and 388 provide five signals T20, T40, T60, T80 and T100, respectively. The signals T20, T40, T60, T80 and T100 may be properly adjusted by the trimmer 390.
A switch network 372 comprises five switches 391, 392, 393, 394 and 395. Control signals are transmitted to the switches 391, 392, 393, 394 and 395 through a switch control line 374. In response to the control signals, the signals T20, T40, T60, T80 and T100 are selectively inputted into a positive input terminal of a comparator 362. A current source I provides a current to a sense diode 366 to generate a diode voltage Vdiode. The diode voltage Vdiode is received by the negative input terminal of the comparator 362.
The control logic 368 produces a plurality of control signals. The control signals are sent to the switch network 372 through the switch control line 374 to sequentially close two adjacent switches (e.g. the switch pairs 395 and 394, 394 and 393, 393 and 392, or 392 and 391). Moreover, the high latch enable (HLE) control signal and the low latch enable (LLE) control signal sequentially control the latching of a high latch 364 and a low latch 365. According to the output signals of the high latch 364 and the low latch 365, the temperature range is realized by the control logic 368.
FIG. 3B is a schematic diagram illustrating the relationship between the diode voltage Vdiode and the temperature. As shown in FIG. 3B, the diode voltage Vdiode decreases with increasing temperature.
FIG. 3C is a schematic timing waveform diagram illustrating the control signals S1, S2, S3, S4 and S5, the HLE control signal and the LLE control signal processed by the temperature detecting device of FIG. 3A. In a case that the temperature ranges between 100 degrees (in Celsius) and 80 degrees, the control signal S1 is sent to the switch network 372 through the switch control line 374 to close the switch 395, so that the signal T100 and the diode voltage Vdiode are inputted into the comparator 362. The comparing result of the comparator 362 is stored in the high latch 364. Sequentially, the control signal S2 is sent to the switch network 372 through the switch control line 374 to close the switch 394, so that the signal T80 and the diode voltage Vdiode are inputted into the comparator 362. The comparing result of the comparator 362 is stored in the low latch 365. If the level states of the high latch 364 and the low latch 365 are respectively “0” and “1”, it is determined that the temperature ranges between 100 degrees and 80 degrees. Whereas, if the level states of the high latch 364 and the low latch 365 are respectively “0” and “0”, it is determined that the temperature is lower than 80 degrees. Whereas, if the level states of the high latch 364 and the low latch 365 are respectively “1” and “1”, it is determined that the temperature is higher than 100 degrees.
Similarly, for any temperature range, the control logic 368 may produce two corresponding control signals S1˜S5 to control two adjacent switches. If the level states of the high latch 364 and the low latch 365 are respectively “0” and “1”, it is determined that the temperature ranges within the corresponding temperature range. On the other hand, if the level states of the high latch 364 and the low latch 365 are not respectively “0” and “1”, the similar process should be done for another temperature range.
Generally, the temperature signal used in a digital circuit should be binary temperature signal. Since the conventional temperature detecting device fails to directly output the binary temperature signal, an additional encoder is necessary to convert the thermometer code into a binary code.
Therefore, there is a need of providing a temperature detecting device and a temperature detecting method for directly outputting a binary code in order to obviate the drawbacks encountered from the prior art.